Trucrux Inc

Testing SPI

Testing Inbuild SPI #

Trucrux provides spidev_test pre-compiled for easy testing.

Follow Customizing Source Code part of LINUX KERNEL CONFIGURATION.

Go to source code of linux-trucrux and copy the file spidev_test file in device.

Then create a LOOPBACK by shorting MISO and MOSI pins. Refer Carrier Board datasheet.pdf for pinouts.

Now simply run the below command on the device.

root@imx8mq-trux-q01:~# chmod 777 spidev_test
root@imx8mq-trux-q01:~# ./spidev_test -v -D /dev/spidev0.2

and the output should be as follows.

without LOOPBACK

root@imx8mq-trux-q01:~# ./spidev_test -v -D /dev/spidev0.2
spi mode: 0x0
bits per word: 8
max speed: 500000 Hz (500 KHz)
TX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D |......@.........................|
RX | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................................|

with LOOPBACK

root@imx8mq-trux-q01:~# ./spidev_test -v -D /dev/spidev0.2
spi mode: 0x0
bits per word: 8
max speed: 500000 Hz (500 KHz)
TX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D |......@.........................|
RX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D |......@.........................|

Using multiple SPI CS lines #

The i.MX8M SPI controllers support up to 4 chip select lines.
In the example below GPIO1_12 and GPIO1_15 are used to control CS0 and CS1 respectively.
When selecting CS GPIO pins make sure they are not used to control other peripherals

You can edit imx8mq-trux-8MDVP.dtsi

&ecspi1 {
	#address-cells = <1>;
	#size-cells = <0>;
 	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
        cs-gpios = <&gpio1 12 0>,
                   <&gpio1 15 0>;
        fsl,spi-num-chipselects = <2>;
	status = "okay";

        chip1@0 {
               reg = <0>;
               ...
        };

        chip2@1 {
               reg = <1>;
               ...
        };
};
&iomuxc {
 		pinctrl_ecspi1: ecspi1grp {
			fsl,pins = <
				MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	        0x11
				MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	        0x11
				MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	        0x11
				MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12	        0x11
                                 MX8MQ_IOMUXC_GPIO1_I015_GPIO1_IO15	        0x11
			>;
		};
                ...
	};
};